Methods for reducing charge effects and separation forces in nanoimprint

ABSTRACT

The present invention relates to methods to reduce release force caused by tribo-charge. The invented mold is termed as MicroE mold and substrate is termed as MicroE substrate. The addition of conductive thin coatings (less than 10 nm and approaching monolayer coating) onto surface of insulating mold or substrate provides a reduction of the separation force caused by tribo-electric charge. The MicroE mold and MicroE substrate are specifically good for a lithographic method that involves contact between mold and substrate, or between mold and thin film carried on substrate, and used for creation and replication of ultra-fine structures (sub-25 nm) as well as millimeter scale. The present invention is particularly but not exclusively applied to any contact lithographic method.

CROSS-REFERENCING

This application is also claims the benefit of: provisional applicationSer. No. 61/801,424, filed Mar. 15, 2013 (NSNR-004PRV), provisionalapplication Ser. No. 61/801,096, filed Mar. 15, 2013 (NSNR-005PRV),provisional application Ser. No. 61/800,915, filed Mar. 15, 2013(NSNR-006PRV), provisional application Ser. No. 61/793,092, filed Mar.15, 2013 (NSNR-008PRV), provisional Application Ser. No. 61/801,933,filed Mar. 15, 2013 (NSNR-009PRV), provisional Application Ser.No.61/794,317, filed Mar. 15, 2013 (NSNR-010PRV), provisionalapplication Ser. No. 61/802,020, filed Mar. 15, 2013 (NSNR-011PRV) andprovisional application Ser. No. 61/802,223, filed Mar. 15, 2013(NSNR-012PRV), all of which applications are incorporated by referenceherein for all purposes.

BACKGROUND

Nanoimprint needs reduction charge effects and separation forces.

SUMMARY

The following brief summary is not intended to include all features andaspects of the present invention, nor does it imply that the inventionmust include all features and aspects discussed in this summary.

The invention is related to the methods and apparatus to reduce chargeeffects and separation forces in nanoimprint, hence improve nanoimprintquality.

BRIEF DESCRIPTION OF THE DRAWINGS

The skilled artisan will understand that the drawings, described below,are for illustration purposes only. The drawings are not intended tolimit the scope of the present teachings in any way. Some of thedrawings are not in scale.

FIG. 1 Schematics of a nanoimprint mold and a substrate, each has threelayers. The table shows which layer should be grounded. The bestapproach is the ground layer as close to the contact surface aspossible.

FIG. 2 Schematics of the possibility of grounding.

FIG. 3 (A) the cross section view of one type of MicroE mold that has aninsulating body. (B) the cross section view of one type of MicroE moldthat has a conductive body. And (C) the cross section view of MicroEsubstrate that carries a thin film as resist.

FIG. 4 is the experimental results comparing the effect in reducing theseparation force between planar MicroE mold and conventional mold.

FIG. 5 The experimental results comparing the effect in reducing theseparation force between the nanostructured MicroE mold and conventionalmold, showing the advantage of the MicroE mold.

Corresponding reference numerals indicate corresponding parts throughoutthe several figures of the drawings. It is to be understood that thedrawings are for illustrating the concepts set forth in the presentdisclosure and are not to scale.

Before any embodiments of the invention are explained in detail, it isto be understood that the invention is not limited in its application tothe details of construction and the arrangement of components set forthin the following description or illustrated in the drawings.

DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS

The following detailed description illustrates some embodiments of theinvention by way of example and not by way of limitation.

This disclosure incorporates by reference the following disclosures:U.S. application Ser. No.13/838,600, filed Mar. 15, 2013 (NSNR-003), andU.S. application Ser. No. 13/699,270, filed Jun. 13, 2013 (NSNR-001).

The invention is related to nanoparticle structures,

The methods invented, that can reduce the charge effects in nanoimprint,comprising

-   -   1. Having a substrate with a thin conducting layer up close to        the surface;    -   2. Having a mold with conducting layer close to surface,        therefore the contact charge between the mold and the substrate        will be reduced.

In another approach, when separating the mold and substrate, an ion beamdischarge will be used to discharge the charge between the mold andsubstrate. The separation will start from edge and gradually open up.

the deposit metal film on the surface of the mold, in thin resist withgood conductivity using light after imprint to increase conductivity ofthe resist, if resist is photoconductive.

The present invention relates to the strength of electric field betweenmold and substrate in their separation. For any lithography thatinvolves contact, tribo-electricity is generated after lithography maskseparates from substrate. The tribo-charge on the surface of mold andthin film on substrate give rise to electric field between them. Theelectric field caused attraction between mold and substrate and enlargesthe mold-substrate separation force.

The present invention relates to the method to reduce the strength ofelectric field between mold and substrate in their separation. Themethod is to coat a thin conductive layer (thinner than 10 nm andapproaching monolayer) onto insulating mold surface and onto surface ofsubstrate carrying on insulating thin film. The image charge induced inthe process of mold-substrate separation reduces the strength ofelectric field in the gap between them. The description of conductiveand insulating material may be described as follows. A conductivecoating or material is one whose relaxation time is shorter than thetime taken to separate mold from substrate. The relaxation time ofmaterial is the product of R and C, where R is the material resistanceand C is the material capacitance. In addition, the relaxation timeequals to ε₀/σ a for metallic materials and ε_(r)ε₀/σ for semiconductingor dielectric materials, where ε₀ and ε_(r) are vacuum permittivity andrelative dielectric constant respectively, and σ is conductivity ofmaterial. Setting t as the process time to release mold from substrate,by conductive materials, it meant that conductivity of materials islarger than ε/t, while insulating materials means materials whoseconductivity smaller than ε/t. For example, if it takes 1 ms to separatemold from substrate, then materials and coating film having aconductivity larger than 10⁻⁶ S/m are conductive materials. By the sameprinciple, conductivity of insulating materials is smaller than 10⁻⁶S/m.

FIG. 3A shows MicroE mold 1 that has insulating body 2 as defined above.Surface of MicroE mold is coated by a thin conductive layer 3. On top of3 deposited a layer of release layer that has non-stick functionality asUS 2001/6309580 (Stephen Chou). The conductive coating material can be,but not limited to, metallic, semi-metallic, metallic and semi-metallicoxides, carbides and nitrides, polymeric, semiconductors, glass,ceramic, dielectrics and composites, as long as the charge relaxationtime of materials (RC time) is shorter than time t used in separation.The thickness of the coating is thinner than 10 nm and approachesmonolayer thickness until the conductivity of thin film significantlydrop and the film transforms to insulator. The insulating body 2 in FIG.1A has a relaxation time longer than separation time t, particularly butnot exclusively includes glass, ceramic, polymeric materials, oxides,carbides and nitrides dielectrics and composites.

FIG. 3B shows another type of MicroE mold 5. It has a conductive body 6,on top of which coated by anti-sticky layer 8 as disclosed in US2005/0146079 (Stephen Chou). The conductive thin layer 7 between 6 and 8is coated only when the surface of MicroE mold body 6 does not providesufficient bonds to anti-sticky layer 8 and performs to assist molecularbonding. The materials of conductive layer coating includes but notlimited to metallic, semi-metallic, metallic and semi-metallic oxides,carbides and nitrides, polymeric, semiconductors, glass, ceramic,dielectrics and composites.

FIG. 3C shows the MicroE substrate 9. It consists of a substrate body10. A thin conductive layer 11 is coated on the surface of substratebody 10 and carries the thin film 12 known as resist in lithographymethods. Examples of thin layer 11 are but not limited to metallic,semi-metallic, metallic and semi-metallic oxides, carbides and nitrides,polymeric, semiconductors, glass, ceramic, dielectrics and composites.Thin film 12 may comprise thermally or optically curable polymermaterial or any other materials that may change materials propertyfollowing the change of environment (e.g. heating, mechanicallyre-shaping, optically shinning, electron beam treating).

Furthermore, light can be used to reduce the tribo-electric charge.

Although the foregoing invention has been described in some detail byway of illustration and example for purposes of clarity ofunderstanding, it is readily apparent to those of ordinary skill in theart in light of the teachings of this invention that certain changes andmodifications may be made thereto without departing from the spirit orscope of the appended claims.

Accordingly, the preceding merely illustrates the principles of theinvention. It will be appreciated that those skilled in the art will beable to devise various arrangements which, although not explicitlydescribed or shown herein, embody the principles of the invention andare included within its spirit and scope. Furthermore, all examples andconditional language recited herein are principally intended to aid thereader in understanding the principles of the invention and the conceptscontributed by the inventors to furthering the art, and are to beconstrued as being without limitation to such specifically recitedexamples and conditions. Moreover, all statements herein recitingprinciples, aspects, and embodiments of the invention as well asspecific examples thereof, are intended to encompass both structural andfunctional equivalents thereof. Additionally, it is intended that suchequivalents include both currently known equivalents and equivalentsdeveloped in the future, i.e., any elements developed that perform thesame function, regardless of structure. The scope of the presentinvention, therefore, is not intended to be limited to the exemplaryembodiments shown and described herein. Rather, the scope and spirit ofpresent invention is embodied by the appended claims.

EXAMPLES

An example of MircroE mold body consists of silicon dioxide backed bysilicon bulk. The conductive layer used in one experiment is Ti. A 5 nmTi coating layer was coated onto the surface of MicroE mold body usingelectron beam sputtering machine. A mold release layer of 1H, 1H, 2H,2H-perfluorodocecyltrichlorosilane (commercially available as a 97%solids solution) is bonded to the surface of Ti and used as ananti-release layer.

The MicroE mold was then applied in nanoimprint lithography US1998/5772905 (Stephen Y Chou). In nanoimprint lithography, the siliconsubstrate carries a commercially thermal-plastic resist (NX-1025) thatwould get intimate get with the MicroE mold and get separatedafterwards.

FIG. 4 shows experimental results on peak separation force comparingMicroE mold with conventional mold without 5 nm conductive coating. Inthe experiment, MicroE mold is planar. A 8× reduction in separationforce is obtained by using MicroE mold with a bulky silicon dioxide bodyand nanomprinted onto thermal-plastic resist on silicon substrate.

FIG. 5. shows experimental results on peak separation force comparingMicroE mold with conventional mold without 5 nm conductive coating. Inthe experiment, MicroE mold has 200 nm pitch 160 nm deep grating and 1micro-meter pitch, 160 nm deep grating feature size. The substrate usedis silicon substrate that carries NX-1025 thermal-plastic resist. A 3×reduction in separation force is obtained for MicroE mold with 1micron-meter pitch grating and 2× reduction for the one with 200 nmpitch grating features.

Table 1 shows results on measured charge density on as-imprinted thinfilm on substrate as a function of thickness of SiO2 middle layer.

TABLE 1 Imprint Charge Substrate Type Surface Potential (V) density(C/m²) Si* T-NIL 19 2.5 × 10⁻³ 1 μm SiO₂/Si* T-NIL 80 2.2 × 10⁻³ 2.5 μmSiO₂/Si* T-NIL 179 2.3 × 10⁻³ 5 μm SiO₂/Si* T-NIL 347 2.2 × 10⁻³ 10 μmSiO₂/Si* T-NIL 388 1.3 × 10⁻³ 500 μm SiO₂/Cr** T-NIL 1600 1.1 × 10⁻⁴Fused Silica T-NIL 27,000 1.0 × 10⁻⁵ UV-NIL 20,000 7.5 × 10⁻⁶ *Si wasgrounded during separation and surface potential measurement **Cr wasgrounded during separation and surface potential measurement

What is claimed is:
 1. A method to reduce tribo-electricity effectbetween a mold and a resist on a substrate and improve mold separationand/or nanoimprint quality, comprising: (a) adding a conducting layer onthe mold; (b) adding a conducing layer on the substrate; and (c)grounding the conducting layer on the mold and the conducting layer onthe substrate, thereby reducing the tribo-electricity effect between amold and a resist on a substrate, and/or improving the mold separationand/or nanoimprint quality.